There is an ongoing demand in the manufacturing of NAND memory cell arrangements to shrink structures and to store more bits in each memory cell. Due to shrinking, the electrical resistance (R) and the electrical capacitance (C) of all global structures (such as, e.g., a global word line (WL) or a global bit line (BL)) is increasing. Furthermore, due to the desired increasing number of bits stored in one memory cell, the number of read operations and verify operations (e.g., to verify a level to be programmed into a memory cell) is growing drastically (˜quadratic). Usually, the number of required programming pulses in a program operation is increasing in a linear manner with the number of memory cell levels to be programmed. For each verify operation (which is illustratively also a read operation) as well as for each programming pulse (due to inhibit), e.g., the global bit lines (GBL) have to be charged up.
During a read/verify operation, the GBL's have to be discharged through the memory cell strings (each memory cell string including a plurality of serially source-to-drain coupled memory cells) to achieve a detectable voltage drop on the respective GBL. The (maximum achievable) memory cell string current (at a given pass voltage) is reduced due to the shrinking and with the number of provided memory cells in a memory cell string. The pass voltage is limited due to read disturb reasons. The maximum allowed discharge current may only be a fraction of the achievable current, due to minimize back pattern effects (later on programmed bits in the same string will reduce the read current of the bit of interest due to its increased resistivity). Due to the fact that the “Vt” measurement (more generally the measurement of the memory cell's programming state) is performed by using a certain string current that causes a voltage drop on the corresponding bit line; this current reduction will be interpreted by the sensing scheme as a so-called Vt shift and, when exceeding a read level, as a change of the memory cell's programming state. Thus, the used string current should be small due to accuracy reasons with respect to “back pattern”. Therefore, the discharging time would increase to realize the same voltage drop on the bit line “BL”. One way to address issues in terms of speed (R*C and discharge time ˜C/string current) and power consumption would be to reduce the length of the GBL's (because the values of R and C are proportional to the length of the GBL's). However, in a conventional memory cell arrangement, on each (or on each second) GBL, there is connected one “Page buffer” (in the following also referred to as a page buffer circuit), that is latching and storing data of all levels in the memory cell related to it.
A page buffer circuit is a huge structure (e.g., for multi-level cell (MLC) devices), because each bit information (of at least one memory cell associated with this page buffer, for “pseudo block programming” and imprint of neighbored cells or more information or/and some soft information) must be somehow stored (e.g., in a latch of the page buffer circuit). From the perspective of array efficiency, as little space as possible required to implement the buffer circuits on the chip is desired (from a performance point of view, at least one page buffer circuit for each bit of a memory cell page is provided).